In recent years, various electronic apparatuses have wireless communication functions. A wireless communications system includes a frequency synthesizer (a phase-locked loop) to generate a signal of a desirable frequency. Such a frequency synthesizer includes an analog PLL or a digital PLL (ADPLL; all-digital phase locked loop) (for example, refer to PTL 1 to PTL 3). In a case where the frequency synthesizer includes the digital PLL, it is possible, for example, to reduce a layout area of an integrated circuit and to decrease power consumption, as compared with a case where the frequency synthesizer includes the analog PLL.
For such a digital PLL, various techniques of reducing phase noise of signals to be generated are disclosed. For example, NPL 1 discloses a circuit that generates signals of four phases on the basis of a signal outputted from an oscillating circuit, and feeds back one of the signals of four phases.